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FinFET based SRAM cells design in various topologies using different power reduction techniques

Manda Damodhar Rao, Yellapu Venkata Narayana, Varre Venkata Kanaka Durga Vara Prasad

Abstract


In Very Large Scale Integration (VLSI) design, device scaling is restricted due to subthreshold swing limitations and short channel effects. This article discusses the role of different power reduction techniques in the implementation of 14 nm fin-shaped field-effect transistor (FinFET) centered static random access memory (SRAM) cells with good subthreshold swing and reduced short channel effects (SCE).  Dynamic threshold and power gating are incorporated in SRAM cells to advance the memory cell performance by reducing static power dissipation in standby mode. The power analysis was performed on different SRAM cells with different transistor count i.e., 6, 7, 8, and 9. The performance of SRAM cell is analysed in power dissipation and is reduced by 20% using power gating method and in dynamic threshold it is reduced to nano watts due to less leakage power.


Keywords


FinFET; SRAM cell; power reduction techniques

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References


1. Sinangil ME, Lin YT, Liao HJ, Chang J. A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM compiler design using a 12T write contention and read upset free Bit-Cell. IEEE Journal of Solid-State Circuits 2019; 54(4): 1152–1160. doi: 10.1109/JSSC.2019.2895236

2. Gupta M, Gupta K, Pandey N. Comparative analysis of the design techniques for low leakage SRAMs at 32nm. Microprocessors and Microsystems 2021; 85: 104281. doi: 10.1016/j.micpro.2021.104281

3. Yadav N, Kim Y, Li S, Choi KK. Stable, low power and bit-interleaving aware SRAM memory for multi-core processing elements. Electronics 2021; 10(21): 2724. doi: 10.3390/electronics10212724

4. Hsieh CY, Fan ML, Hu VPH, et al. Independently-controlled-gate FinFET Schmitt trigger sub-threshold SRAMs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems2012; 20(7): 1201–1210. doi: 10.1109/TVLSI.2011.2156435

5. Oh TW, Jeong H, Kang K, et al. Power-gated 9T SRAM cell for low-energy operation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2017; 25(3): 1183–1187. doi: 10.1109/TVLSI.2016.2623601

6. Damodhar RM, Narayana YV, Prasad VVKDV. Ultra low power offering 14 nm bulk double gate FinFET based SRAM cells. Sustainable Computing: Informatics and Systems 2022; 35: 100685. doi: 10.1016/j.suscom.2022.100685

7. Akkala AG, Venkatesan R, Raghunathan A, Roy K. Asymmetric underlapped Sub-10-nm n-FinFETs for high-speed and low-leakage 6T SRAMs. IEEE Transactions on Electron Devices 2016; 63(3): 1034–1040. doi: 10.1109/TED.2015.2512227

8. Moradi F, Gupta SK, Panagopoulos G, et al. Asymmetrically doped FinFETs for low-power robust SRAMs. IEEE Transactions on Electron Devices 2011; 58(12): 4241–4249. doi: 10.1109/TED.2011.2169678

9. Pal PK, Kaushik BK, Dasgupta S. Design metrics improvement for SRAMs using symmetric Dual-k Spacer (SymD-k) FinFETs. IEEE Transactions on Electron Devices 2014; 61(4): 1123–1130. doi: 10.1109/TED.2014.2304711

10. Pal PK, Kaushik BK, Dasgupta S. High-performance and robust SRAM cell based on asymmetric Dual-k Spacer FinFETs. IEEE Transactions on Electron Devices 2013; 60(10): 3371–3377. doi: 10.1109/TED.2013.2278201

11. Shin K, Choi W, Park J. Half-select free and bit-line sharing 9T SRAM for reliable supply voltage scaling. IEEE Transactions on Circuits and Systems I: Regular Papers 2017; 64(8): 2036–2048. doi: 10.1109/TCSI.2017.2691354

12. Wu YT , Ding F, Connelly D, et al. Simulation-based study of high-density SRAM voltage scaling enabled by inserted-oxide FinFET technology. IEEE Transactions on Electron Devices 2019; 66(4): 1754–1759. doi: 10.1109/TED.2019.2900921

13. Song T, Rim W, Park S, et al. A 10 nm FinFET 128 Mb SRAM with assist adjustment system for power, performance, and area optimization. IEEE Journal of Solid-State Circuits 2017; 52(1): 240–249. doi: 10.1109/JSSC.2016.2609386

14. Jeong H, Kim TH, Park CN, et al. A wide-range static current-free current mirror-based LS with logic error detection for near-threshold operation. IEEE Journal of Solid-State Circuits 2021; 56(2): 554–565. doi: 10.1109/JSSC.2020.3014954

15. Guler A, Jha NK. Three-dimensional monolithic FinFET-based 8T SRAM cell design for enhanced read time and low leakage. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2019; 27(4): 899–912. doi: 10.1109/TVLSI.2018.2883525

16. Almeida RB, Marquesa CM, Butzena PF, et al. Analysis of 6T SRAM cell in sub-45 nm CMOS and FinFET technologies. Microelectronics Reliability 2018; 88–90: 196–202. doi: 10.1016/j.microrel.2018.07.134

17. Turi MA, Delgado-Frias JG. Full-VDD and near-threshold performance of 8T FinFET SRAM cells. Integration 2017; 57: 169–183. doi: 10.1016/j.vlsi.2016.12.003

18. Joshi RV, Ziegler MM, Wetter H. A low voltage SRAM using resonant supply boosting. IEEE Journal of Solid-State Circuits 2017; 52(3): 634–644. doi: 10.1109/JSSC.2016.2628772

19. Wang CC, Sangalang RGB, Tseng IT. A single-ended low power 16-nm FinFET 6T SRAM design with PDP reduction circuit. IEEE Transactions on Circuits and Systems II: Express Briefs 2021; 68(12): 3478–3482. doi: 10.1109/TCSII.2021.3123676

20. Abbasian E, Gholipour M. Design of a Schmitt-trigger-based 7T SRAM cell for variation resilient low-energy consumption and reliable internet of things applications. AEU-International Journal of Electronics and Communications 2021; 138: 153899. doi: 10.1016/j.aeue.2021.153899

21. Pasandi G, Fakhraie SM. An 8T low-voltage and low-leakage half-selection disturb-free SRAM using Bulk-CMOS and FinFETs. IEEE Transactions on Electron Devices 2014; 61(7): 2357–2363. doi: 10.1109/TED.2014.2321295

22. Frustaci F, Blaauw D, Sylvester D, Alioto M. Approximate SRAMs with dynamic energy-quality management. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2016; 24(6): 2128–2141. doi: 10.1109/TVLSI.2015.2503733

23. Oh TW, Jeong H, Park J, Jung SO. Pre-charged local bit-line sharing SRAM architecture for near-threshold operation. IEEE Transactions on Circuits and Systems I: Regular Papers 2017; 64(10): 2737–2747. doi: 10.1109/TCSI.2017.2702587

24. Sheu MH, Morsalin SMS, Tsai CM, et al. Stable local bit-line 6 T SRAM architecture design for low-voltage operation and access enhancement. Electronics 2021; 10(16): 685. doi: 10.3390/electronics10060685

25. Yang Y, Park J, Song SC, et al. Single-ended 9T SRAM cell for near-threshold voltage operation with enhanced read performance in 22-nm FinFET technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2015; 23(11): 2748–2752. doi: 10.1109/TVLSI.2014.2367234

26. Sharma P, Gupta S, Gupta K, Pandey N. A low power subthreshold Schmitt trigger based 12T SRAM bit cell with process-variation-tolerant write-ability. Microelectronics Journal 2020; 97: 104703. doi: 10.1016/j.mejo.2020.104703

27. Bagheriye L, Toofan S, Saeidi R, Moradi F. Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing. Integration 2019; 65: 128–137. doi: 10.1016/j.vlsi.2018.11.011

28. Mohammed MU, Nizam A, Ali L, Chowdhury MH. FinFET based SRAMs in Sub-10nm domain. Microelectronics Journal 2021; 114: 105116. doi: 10.1016/j.mejo.2021.105116

29. Goel A, Gupta SK, Roy K. Asymmetric drain spacer extension (ADSE) FinFETs for low-power and robust SRAMs. IEEE Transactions on Electron Devices 2011; 58(2): 296–308. doi: 10.1109/TED.2010.2090421

30. Monteiro C, Takahashi Y. Ultra-low-power FinFETs-based TPCA-PUF circuit for secure IoT devices. Sensors 2021; 21(24): 8302. doi: 10.3390/s21248302

31. Kim Y, Patel S, Kim H, et al. Ultra-low power and high-throughput SRAM design to enhance AI computing ability in autonomous vehicles. Electronics 2021; 10(3): 256. doi: 10.3390/electronics10030256




DOI: https://doi.org/10.32629/jai.v7i1.976

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Copyright (c) 2023 Manda Damodhar Rao, Yellapu Venkata Narayana, Varre Venkata Kanaka Durga Vara Prasad

License URL: https://creativecommons.org/licenses/by-nc/4.0/